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Altera Quartus II v14.1

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Altera最新版设计软件Quartus II软件v14.0引入了最新开发的快速重新编译特性,这一使用方便的设计流程进一步缩短了编译时间。此外,Quartus II软件v14.0还包括了下一代设计空间管理器(DSE)——使用方便的一款设计优化工具,以及增强了Qsy,Altera的系统集成工具。该版本也实现了Cyclone® V SoC和Arria V SoC的最终时序模型。

Altera的最新版本设计软件——Quartus® II软件Arria® 10版v14.0,为业界提供最先进的设计环境,支持您马上开始20 nm Arria 10 FPGA和SoC设计。使用这一全面的设计套装,您会体验到编译时间比竞争产品平均快2.5倍,设计性能高出一个速率等级。Quartus II软件Arria 10版v14.0是目前20 nm唯一可马上进行设计而且最全面的设计软件。

采用Quartus II软件Arria 10版v14.0,您可以使用最终引脚输出和时序模型完成您的电路板布局,达到时序收敛。电路板设计人员现在可以在工程样片上使用最终引脚输出,在系统原型设计上使用早期功耗估算器模型。马上下载Quartus II软件Arria 10版v14.0,开始您的设计!

IP Core支持

Quartus II软件Arria 10版v14.0对20 nm最佳的知识产权(IP)内核提供了全面补充以加速设计周期。Altera还针对Arria 10 FPGA和SoC,优化了其同类最佳的IP内核,包括100G Ethernet、300G Interlaken / Interlaken Look-Aside,以及PCI Express® Gen3 IP内核。在Altera的Arria 10 FPGA和SoC中实现时,这些同类最佳的IP内核实现了FPGA业界最佳的性能。如果要了解详细信息,请访问 Quartus II软件Arria 10版v14.0新增IP特性 页面。

SoC支持

Quartus II软件Arria 10版v14.0具有全部新的硬核处理器系统(HPS) Qsys MegaWizard的特性,使得设计人员能够配置Arria 10 SoC HPS中的处理器和外设。电路板设计人员通过最终引脚列表以及利用Arria 10 FPGA和SoC器件之间完整的引脚兼容性可以开始对 Arria 10 SoC 进行原型PCB设计。软件应用于开发人员可以利用28 nm Cyclone V和Arria V SoC以及20 nm Arria 10 SoC之间的代码兼容性的优势。他们可以将28 nm SoC中广泛的应用代码、工具、操作系统支持,以及开发套件重新用于加速软件开发和原型设计。

Arria 10 FPGA和SoC简介

在20 nm,Altera的Arria 10 FPGA和SoC是性能最好的,性能比竞争器件高出一个速率等级。Arria 10 FPGA和SoC的功耗比前一代FPGA和SoC低40%,具有业界唯一的硬核浮点数字信号处理(DSP)模块。如果需要了解详细信息,请访问 Arria 10 FPGA和SoC 网页。

Quartus是Altera公司推出的一种可编程逻辑器件电子设计自动化开发软件。它可以识别电路的Verilog或VHDL高级硬件描述语言表述,或读取指定格式的线路图;进而完成逻辑仿真、功能验证、逻辑综合等任务,对器件的进行编程,即将设计项目转换到实际的硬件。该软件提供了逻辑电路的可视化设计以及向量波形的仿真等功能。


Altera version 14.1 | 30.1 Gb

Altera Corporation released its Quartus II software version 14.1 featuring expanded support for Arria 10 FPGAs and SoCs, the FPGA industry’s only devices with hardened floating point DSP blocks and the industry’s only 20 nm SoC FPGAs that integrate ARM processors. 

Altera’s latest software release provides immediate support for the hardened floating point DSP blocks integrated in Arria 10 FPGAs and SoCs. Users can choose between three unique DSP design entry flows and achieve up to an industry-leading 1.5 TFLOPS of DSP performance. The software also includes several optimizations that improve designer productivity by accelerating Arria 10 FPGA and SoC design time.

Integrated IEEE 754-compliant, floating-point DSP blocks in Arria 10 FPGAs and SoCs deliver unparalleled levels of DSP performance, designer productivity and logic efficiency. The Quartus II software version 14.1 offers an advanced tool flow with multiple design entry options that target the hardened floating point DSP blocks and allow users to quickly design and deploy solutions that address a range of computationally intensive applications, in areas such as high-performance computing (HPC), radar and medical imaging. These design flows include OpenCL for software programmers, DSP Builder for model-based designers and hardware description language (HDL) flows for traditional FPGA designers. Unlike a soft implementation, hardened floating point DSP blocks do not consume valuable logic resources for floating point operations.

Additional Features in Quartus II Software version 14.1 Include:

- An enhanced Design Space Explorer II (DSE II) tool for faster timing closure, which delivers real-time status and reporting data to users. The data can be used to do side-by-side comparisons of multiple compiles being generated simultaneously on compute farms.
- An optimized centralized IP catalog and improved graphical user interface (GUI) helps to store and easily find all custom IP in a single location.
- Additional support for Altera’s new non-volatile MAX 10 FPGAs, which feature dual-configuration flash, analog and embedded processing capabilities in a small-form-factor, low-cost, instant-on programmable logic device.
- Enhancements to the JNEye serial link analysis tool further simplify board-level design and planning. The JNEye tool, along with Arria 10 silicon models, is able to simulate transmission line models and estimate insertion loss and cross talk parameters in Arria 10 designs.

Additional information about the latest features offered in Quartus II software v14.1 is available on the What's New in Quartus II Software version 14.1

About Altera

Altera programmable solutions enable designers of electronic systems to rapidly and cost effectively innovate, differentiate and win in their markets. Altera offers FPGAs, SoCs, CPLDs, ASICs and complementary technologies, such as power management, to provide high-value solutions to customers worldwide.

Name: Altera Quartus II 
Version: (64bit) 14.1.0.186
Home: www.altera.com
Interface: english
OS: Windows / Linux
Size: 30.1 Gb


#Win版本首先安装Quartus II 14.1软件:
# 第一步: 用Quartus_II_14.1破解器.exe破解C:\altera\14.1\quartus\bin64下的gcl_afcq.dll文件(运行Quartus_II_14.1破解器.exe后,直接点击gcl_afcq.dll右边的查找按钮,然后选中bin64文件夹中的gcl_afcq.dll,点击“打开”,继续点击“下一步”,破解第一个dll的加密点,最后点击“完成”破解第二个dll的加密点,第一步完成。----默认安装时,gcl_afcq.dll路径在C:\altera\14.1\quartus\bin64下)。

#第二步: 把license.dat里的XXXXXXXXXXXX 用你的网卡号替换(在Quartus II 14.1的Tools菜单下选择License Setup,下面就有NIC ID)。

#第三步: 在Quartus II 14.1的Tools菜单下选择License Setup,然后选择License file,最后点击OK。

#注意:license文件存放的路径名称不能包含汉字和空格,空格可以用下划线代替。
#备注:Quartus II从14.0开始只有64位版本了,此破解器在Windows 7和8的64位操作系统下验证过了,没有问题!Windows XP和Vista因为微软都放弃了,所以没有验证,理论上64位的XP和Vista也许可以正常使用,不过还是尽量用64位的Windows 7或者8。

安装Quartus II 14.1后(Linux版本),方法如下:

# 第一步: 把Crack_QII_14.1_Linux.zip里面的libgcl_afcq.so和libsys_cpt.so文件分别解压缩后,替换/root/altrea/14.1/quartus/linux64里面的同名文件,这样2个so文件里面的加密点就全部被破解了。
#第二步: 把license.dat里的XXXXXXXXXXXX 用你的网卡号替换(在Quartus II 14.1的Tools菜单下选择License Setup,下面就有NIC ID)。
#第三步: 在Quartus II 14.1的Tools菜单下选择License Setup,然后选择License file,最后点击OK。
#注意:license文件存放的路径名称不能包含汉字和空格,空格可以用下划线代替。
#在64位操作系统下,默认情况是安装程序会产生64位的桌面快捷方式(启动器),如果少数客户遇到安装程序没有自动产生桌面快捷方式(启动器),就在桌面手动新建一个(在“命令”里面指向/root/altera/14.1/quartus/bin/的quartus)。

 

骏龙科技推荐客户使用Altera官方认可的红帽RHEL 6.x服务器版的64位操作系统,Altera没有推荐的Ubuntu操作系统也可以,不过安装Quartus II时要麻烦一些。

#备注:Quartus II从14.0开始只有64位版本了,此破解器在64位的RHEL 6.5操作系统下验证过,没有问题! 64位的RHEL 5.x操作系统因为Altera很快就要放弃了(14.0现在还是支持64位的RHEL 5.x操作系统的,但是14.1就不支持了,从14.1开始除了支持RHEL 6.x外又增加了RHEL 7.x),所以还是尽量用RHEL 6.x服务器版的64位操作系统。

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