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Cadence INCISIV 14.10.014 Linux

CAX/EDA MilagroVerge 0评论

全球电子设计创新领先企业Cadence设计系统公司近日发布了新版 Incisive® 功能验证平台,再一次为整体验证性能和生产率设定新标准。同时应对知识产权(IP)模块级到芯片级及片上系统(SoC)验证的挑战,Incisive14 平台通过两个新的引擎及附加的自动化功能,把仿真性能提升了一个数量级来加速SoC验证的收敛。

对于 IP 模块级到芯片级的验证,具有以下提升:

· Incisive Formal Verifier和 Incisive Enterprise Verifier中的新的Trident引擎对形式分析的性能提升最高达20倍

· Incisive Enterprise Simulator中新的约束引擎提高 UVM 和 SystemVerilog testbench 仿真速度及在Palladium® 平台的仿真加速速度最高达10倍

· Incisive Debug Analyzer中的对 SystemVerilog 新的支持功能结合独有的 UVM 调试功能和 Incisive 企业仿真器(IES)中 SimVision 调试环境下对探测功能的优化可以降低数据库大小达 10 倍

· 新的 IEEE 1647 e 无需仿真的单元测试,可减少测试平台代码调试时间达30%

对于 SoC 验证,具有以下提升:

· Incisive Enterprise Simulator和Incisive Enterprise Verifier中对X-propagation的全面支持可提高 SoC 复位,低功耗仿真速度达 5 倍

· Incisive 数字混合信号中针对 SystemVerilog IEEE 1800-2012 实数建模支持的新功能选项可提高混合信号仿真速度超过 100 倍。

“我们必须用有限的资源面对不断增长的验证挑战。”安霸公司(Ambarella, Inc.)工程部门副总裁 Chan Lee 指出:“2013 年,我们通过采用X-propagation,帮助我们显著的加快针对复位的仿真性能。Incisive 验证平台提供的附加自动化功能有助于提高我们的验证生产率。”

“验证工程师面临时间和强大验证性能需求方面的压力。Incisive 不但解决了这些问题,同时还超越了每秒原始时钟所赋予的内涵,囊括从Formal Apps、调试到度量指标的分析来加速验证过程的收敛。自动化与集成的结合为我们的客户提供真正的收益,从而减轻 SoC 验证的压力。” Cadence高级验证解决方案研发副总裁 Andy Eliopoulos 说。


14.10.014 | 15.4 Gb

Cadence Design Systems, Inc. has released update of the Incisive functional verification platform, its multi-language simulation fuels testbench automation, low-power, metric driven verification, and mixed-signal verification.

Incisive Enterprise Simulator (IES) provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization. IES is the core engine for low-power verification working closely with Conformal LP, the digital engine for mixed-signal verification working with Virtuoso simulators, the testbench engine for simulation acceleration with Xtreme and Palladium, and the RTL engine working with TLM verification solutions.

More info: http://www.cadence.com/products/fv/enterprise_simulator/

Included:

- Base INCISIV 14.10.001 lnx86
- Hotfix INCISIV 14.10.014 lnx86

Defects fixed in INCISIV14.10.014
================================================================================
CCRID Product Title
------ --------- -----------------------------------------------------------
1294368 AMSD ncelab: *FINTERR when FOR ALL statement defines a module view to be used for all instances of a component
1347443 DBG_ANALYZER wreal with various disciplines are not shown in the IDA TOP browser
1257177 DBG_SIMVISION Renamed created bus not restored on signal load in SimVision
1260708 DBG_SIMVISION SimVision save signals doesnt work if "signed" function used in grouped signals.
1268265 DBG_SIMVISION User created bus not visible when signals reloaded
1294761 DBG_SIMVISION simvision loses information when it (re-) saves a controlfile
1296197 DBG_SIMVISION saving waveform signal not working if you change the datatype to signed
1298938 DBG_SIMVISION Save Signals in simvision does not save Analog Overlay group
1335475 DBG_SIMVISION Simvision Failure: Application initialization failed: not enough arguments for all format specifiers
1341277 DBG_SIMVISION starting simvision in a read-only directory leads to initialization failure
1346165 IEV Support for 'set_parameterized_module_coverage' needed in UNR flow
1350019 IEV IEV proof uses incorrect dimensions for SV struct member defined via VHDL package import
519273 IUS_AMSD Support the notation .* for System Verilog for nets thathave both analog and digital disciplines
849364 IUS_AMSD ncelab: *E,SYERROR in AMS-Ultra sims
1339668 IUS_AMSD Internal error during elaboration in 14.10
1322269 IUS_CORE_ELAB internal error in ncelab due to parameterized classes
1329660 IUS_CORE_ELAB CFMPTC error message when connecting SV struct to VHDL record port
1338098 IUS_CORE_ELAB pth_parse_name - null name
1344564 IUS_CORE_ELAB ncela internal error with sdf and msie
1348839 IUS_CORE_ELAB internal exception with elaborator when black boxing a given level of hierarchy.
1348914 IUS_CORE_ELAB Problem annotating SDF to primary/incremental snapshot
1351464 IUS_CORE_PARSE Bad compilation dependency
1189756 IUS_CORE_SIM ncprofmem.out showing negative memory values
1309870 IUS_CORE_SIM ncsim: *FINTERR when dumping TCF
1342805 IUS_CORE_SIM TCL probe of large design is more than 3.2X slower from 13.2 to 14.1
1351251 IUS_CORE_SIM ncsim Internal Exception with iprof enabled
1287025 IUS_GLS Mismatch between irun log file and sdf statistics file
1343917 IUS_GLS [NCELAB, GLS] Abnormal termination in the middle of netlist elaboration, no message at all
1348510 IUS_GLS ncsim sv_seghandler failure at 0fs + 118
1264707 IUS_LP UPF 1801 restore_condition is not honored according ot the ocs
1330531 IUS_LP Missing isolation rule issue while running hierarchical CPF flow
1340356 IUS_LP Isolation control singal getting replaced by driver in Hierarchical cpf
1342690 IUS_LP Only LSB of bus getting added to a domain with ?boundary_ports and rest excluded.
1267518 IUS_RAND Different results of constraint random generation at SV
1341376 IUS_VPI tracing in schematic causes simvision to become unresponsive
990167 SPECMAN Specman should return error status via NCSim / irun
1314419 SPECMAN Crash opening gtree after contradiction
1347754 SPECMAN Wrong DEPR_GEN_IMPLICIT_INPUT in gen action
1348041 SPECMAN sn_compile.sh: internal error: elib with instance_ignore
1216355 UVM correct the method declarations for vr_set32.copy() and vr_set32.to_string() functions
1267152 UVM vr_ad:provide mechanism to print byte wise operations for update() method
1290195 UVM ncsim fails while resetting
1327604 UVM vr_ad: Grey zone check is taking the wrong previous value
1327631 UVM vr_ad:write_reg using var results with data == 0
1330896 UVM uvm e scoreboard : provide mechanism to support reset scenario
1339264 UVM SystemC Reset Failure in Simvision mode from libuvmapi_generic.so symbol issues
1343045 UVM At gui mode , when I click reset button then ncsim fails
1352618 UVM ncsim: *E,SCK529: insert module failed: after before_end_of_elaboration callback after reset

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.

Name:
Version: 14.10.014
Home: http://www.cadence.com
Interface: english
OS: Linux
Size: 15.4 Gb


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